The final goal of this project is to make a complete ternary computer system.
The end goal has been subdivided into several phases to find out what the various difficulties are encountered and how to move forward.
- Development of the CPU system and ternary memory using only binary components - 100% COMPLETED -;
- Development of an architecture (ISA, Registers, Microarchitecture) - 60% completed -;
- Development of a peripheral system (serial interface, HDMI, Keyboard) - 30% completed -;
- Development of a Monitor;
- Development of a Ternary Operating System;
The CPU implements a RISC instruction set approach, it work with 24 Trit (Ternary Digit) data, 12 Trit addresses and a several Trit control BUS;
Phase 1 is also focused on the design of a set of CPU instructions, in order to define all the basic operations that the CPU will be able to carry out.
The integration will be achieved thanks to a card that supplies two serial ports.